The progress in semiconductor technology means that it is possible to fabricate integrated circuits with a very high integration level. The integration level ranges from VLSI (very large scale integration) through ULSI (ultra large scale integration) up to even higher packing densities. The capacity of a single semiconductor chip rises from formerly a few thousand components through a hundred thousand up to currently millions of components. If we consider DRAM (dynamic random access memories) components, for example, then the capacity of an individual chip of formerly 4 Mbit or 16 Mbit up to 256 Mbit or more can be achieved by virtue of the enormous integration level in fabrication.
Components in integrated circuits, such as transistors or capacitors, have to be miniaturized to an ever greater extent and adapted to the requirements of the integrated circuits. The rising packing density of integrated circuits and the associated miniaturization of the components represent a major challenge to the semiconductor process technology. Thus, during the fabrication of an element or a component of an integrated circuit, care must be taken to ensure that the electrical characteristic quantities and characteristics of the other components on the integrated circuit are not altered or influenced. This means that the fabrication of the components must be achieved with regard to a high packing density, a low generation of heat and a low energy consumption in conjunction with a high reliability and a long lifetime in the fabrication without at the same time having to accept a loss of quality in the function of the component. It is assumed here that these stipulations can be achieved by parallel further development and improvement in the photolithography, the etching processes, the deposition, the ion implantation and the thermal processes, that is to say the five essential aspects of semiconductor technology.
In a known method for fabricating a DRAM cell arrangement (DE 198 45 058 A1), first trenches running essentially parallel to one another are produced in a substrate. The first trenches are filled with isolating structures. By etching with the aid of a strip-type photoresist mask whose strips run transversely with respect to the first trenches, the substrate is etched selectively with respect to the isolating structures, with the result that depressions are produced. Areas of lower regions of the depressions are provided with a capacitor dielectric. A storage node of a storage capacitor is in each case produced in the lower regions of the depressions. Upper source/drain regions of the transistors are produced in such a way that they are in each case arranged between two mutually adjacent depressions and between mutually adjacent isolating structures, and adjoin a main area of the substrate.
Lower source/drain regions of the transistors in the substrate are formed in such a way that they are electrically connected to the storage nodes, with the result that in each case one of the transistors and one of the storage capacitors are connected in series and form a memory cell. By deposition and patterning with masks of conductive material, word lines are produced, which run transversely with respect to the isolating structures above the main area, and, adjoining them, gate electrodes of vertical transistors are produced, which are each arranged in one of the depressions and are electrically insulated from the storage nodes. An insulating layer is produced over the word lines. Insulating spacers are produced on sidewalls of the word lines by depositing material and etching it back. With the aid of a strip-type photoresist mask whose strips run essentially parallel to the isolating structures, etching is effected selectively with respect to the insulating layer and the spacers until the upper source/drain regions are uncovered.
In this case, in the known method, a disadvantage can be seen in the fact that, in the lithographic processes using masks, there is always the problem of the relative alignment (“overlay”) of mask and structure on the wafer. Consequently, the alignment of mask and structure on the wafer becomes a greater problem with increasing miniaturization of the components.
Maskless patterning of a light-sensitive material on a substrate is disclosed in a further known method (U.S. Pat. No. 5,935,763). In this case, the substrate has regions with a different reflection behavior. In this case, a parallel beam of light rays is radiated perpendicularly onto the light-sensitive material. In this case, the incident light is reflected at the reflective regions and therefore radiated back into the light-sensitive material. As a result, the light-sensitive material is exposed perpendicularly above the reflective regions of the substrate and is removed by a later development step, thereby producing an opening in the light-sensitive material which is formed in a self-aligned manner vertically above the reflective region of the substrate.
One disadvantage of the known method can be seen in the fact that a desired structure can be imaged into the light-sensitive material only vertically above the structure represented in the substrate. A substrate structure can therefore be imaged only vertically and true to scale with a scale of 1:1.